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? semiconductor components industries, llc, 2014 august, 2014 ? rev. 6 1 publication order number: mc74lvxt4051/d mc74lvxt4051 analog multiplexer/ demultiplexer high?performance silicon?gate cmos the mc74lvxt4051 utilizes silicon?gate cmos technology to achieve fast propagation delays, low on resistances, and low leakage currents. this analog multiplexer/demultiplexer controls analog voltages that may vary across the complete power supply range (from v cc to v ee ). the lvxt4051 is similar in pinout to the lvx8051, the hc4051a, and the metal?gate mc14051b. the channel?select inputs determine which one of the analog inputs/outputs is to be connected, by means of an analog switch, to the common output/input. when the enable pin is high, all analog switches are turned off. the channel?select and enable inputs are compatible with standard ttl levels. these inputs are over?voltage tolerant (ovt) for level translation from 6.0 v down to 3.0 v. this device has been designed so the on resistance (r on ) is more linear over input voltage than the r on of metal?gate cmos analog switches and high?speed cmos analog switches. features ? select pins compatible with ttl levels ? fast switching and propagation speeds ? low crosstalk between switches ? analog power supply range (v cc ? v ee ) = 3.0 v to 3.0 v ? digital (control) power supply range (v cc ? gnd) = 2.5 to 6.0 v ? improved linearity and lower on resistance than metal?gate, hsl, or vhc counterparts ? low noise ? designed to operate on a single supply with v ee = gnd, or using split supplies up to 3.0 v ? break?before?make circuitry ? these devices are pb?free and are rohs compliant http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. ordering information marking diagrams tssop?16 dt suffix case 948f soic?16 d suffix case 751b lvxt4051g awlyww 1 16 1 16 lvxt4051 = specific device code a = assembly location wl, l = wafer lot y = year ww, w = work week g or = pb?free package (note: microdot may be in either location) lvxt 4051 alyw tssop?16 soic?16 v cc x2 x1 x0 x3 a b c x4 x6 x x7 x5 enable v ee gnd 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 pin assignment
mc74lvxt4051 http://onsemi.com 2 function table pin 16 = v cc pin 8 = gnd pin 7 = v ee common output/input l l l l h h h h x l l h h l l h h x l h l h l h l h x control inputs on channels enable select cba x0 x1 x2 x3 x4 x5 x6 x7 none l l l l l l l l h x = don?t care figure 1. logic diagram single?pole, 8?position plus common off multiplexer/ demultiplexer 3 x analog inputs/outputs channel select inputs 13 14 15 12 1 5 2 4 11 10 9 6 x0 x1 x2 x3 x4 x5 x6 x7 a b c enable ordering information device package shipping ? mc74lvxt4051dg soic?16 (pb?free) 48 units / rail MC74LVXT4051DR2G soic?16 (pb?free) 2500 tape & reel mc74lvxt4051dtg tssop?16 (pb?free) 96 units / rail mc74lvxt4051dtr2g tssop?16 (pb?free) 2500 tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
mc74lvxt4051 http://onsemi.com 3 maximum ratings symbol parameter value unit v ee negative dc supply voltage (referenced to gnd) ?7.0 to +0.5 v v cc positive dc supply voltage (referenced to gnd) (referenced to v ee ) ?0.5 to +7.0 ?0.5 to +7.0 v v is analog input voltage v ee ? 0.5 to v cc + 0.5 v v in digital input voltage (referenced to gnd) ?0.5 to 7.0 v i dc current, into or out of any pin 20 ma t stg storage temperature range ?65 to +150 c t l lead temperature, 1 mm from case for 10 seconds 260 c t j junction temperature under bias +150 c ja thermal resistance soic tssop 143 164 c/w p d power dissipation in still air, soic tssop 500 450 mw msl moisture sensitivity level 1 f r flammability rating oxygen index: 30% ? 35% ul 94?v0 @ 0.125 in v esd esd withstand voltage human body model (note 1) machine model (note 2) charged device model (note 3) 2000 200 1000 v i latchup latchup performance above v cc and below gnd at 125 c (note 4) 300 ma stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. tested to eia/jesd22?a114?a. 2. tested to eia/jesd22?a115?a. 3. tested to jesd22?c101?a. 4. tested to eia/jesd78. recommended operating conditions symbol parameter min max unit v ee negative dc supply voltage (referenced to gnd) ?6.0 gnd v v cc positive dc supply voltage (referenced to gnd) (referenced to v ee ) 2.5 2.5 6.0 6.0 v v is analog input voltage v ee v cc v v in digital input voltage (note 5) (referenced to gnd) 0 6.0 v t a operating temperature range, all package types ?55 125 c t r , t f input rise/fall time v cc = 3.0 v 0.3 v (channel select or enable inputs) v cc = 5.0 v 0.5 v 0 0 100 20 ns/v functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresse s beyond the recommended operating ranges limits may affect device reliability. 5. unused inputs may not be left open. all inputs must be tied to a high?logic voltage level or a low?logic input voltage level. device junction temperature versus time to 0.1% bond failures junction temperature c time, hours time, years 80 1,032,200 117.8 90 419,300 47.9 100 178,700 20.4 110 79,600 9.4 120 37,000 4.2 130 17,800 2.0 140 8,900 1.0 1 1 10 100 1000 failure rate of plastic = ceramic until intermetallics occur figure 2. failure rate vs. time junction temperature normalized failure rate time, years t j = 130 c t j = 120 c t j = 110 c t j = 100 c t j = 90 c t j = 80 c
mc74lvxt4051 http://onsemi.com 4 dc characteristics ? digital section (voltages referenced to gnd) symbo l parameter condition v cc v guaranteed limit unit ?55 to 25 c 85 c 125 c v ih minimum high?level input voltage, channel?select or enable inputs 3.0 4.5 5.5 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 v v il maximum low?level input voltage, channel?select or enable inputs 3.0 4.5 5.5 0.5 0.8 0.8 0.5 0.8 0.8 0.5 0.8 0.8 v i in maximum input leakage current, channel?select or enable inputs v in = 6.0 or gnd 0 v to 6.0 v 0.1 1.0 1.0 a i cc maximum quiescent supply current (per package) channel select, enable and v is = v cc or gnd 6.0 4.0 40 80 a dc electrical characteristics ? analog section symbo l parameter test conditions v cc v v ee v guaranteed limit unit ?55 to 25 c 85 c 125 c r on maximum ?on? resistance v in = v il or v ih v is = ? (v cc ? v ee ) |i s | = 2.0 ma (figure 3) 3.0 4.5 3.0 0 0 ?3.0 86 37 26 108 46 33 120 55 37 r on maximum difference in ?on? res- istance between any two channels in the same package v in = v il or v ih v is = ? (v cc ? v ee ) |i s | = 2.0 ma 3.0 4.5 3.0 0 0 ?3.0 15 13 10 20 18 15 20 18 15 i off maximum off?channel leakage current, any one channel v in = v il or v ih ; v io = v cc or gnd; switch off (figure 3) 5.5 +3.0 0 ?3.0 0.1 0.1 0.5 0.5 1.0 1.0 a maximum off?channel leakage current, common channel v in = v il or v ih ; v io = v cc or gnd; switch off (figure 4) 5.5 +3.0 0 ?3.0 0.2 0.2 2.0 2.0 4.0 4.0 i on maximum on?channel leakage current, channel?to?channel v in = v il or v ih ; switch?to?switch = v cc or gnd; (figure 5) 5.5 +3.0 0 ?3.0 0.2 0.2 2.0 2.0 4.0 4.0 a ac characteristics (input t r = t f = 3 ns) symbo l parameter test conditions v cc v v ee v guaranteed limit unit ?55 to 25 c 85 c 125 c min typ* t bbm minimum break?before?make time v in = v il or v ih v is = v cc r l = 300 c l = 35 pf (figures 11 and 12) 3.0 4.5 3.0 0.0 0.0 ?3.0 1.0 1.0 1.0 6.5 5.0 3.5 ? ? ? ? ? ? ns *typical characteristics are at 25 c.
mc74lvxt4051 http://onsemi.com 5 ac characteristics (c l = 50 pf, input t r = t f = 3 ns) symbo l parameter v cc v v ee v guaranteed limit unit ?55 to 25 c 85 c 125 c min typ max min max min max t plh , t phl maximum propagation delay, channel?select to analog output (figures 15 and 16) 2.5 3.0 4.5 3.0 0 0 0 ?3.0 40 28 23 23 45 30 25 25 50 35 30 28 ns t plz , t phz maximum propagation delay, enable to analog output (figures 13 and 14) 2.5 3.0 4.5 3.0 0 0 0 ?3.0 40 28 23 23 45 30 25 25 50 35 30 28 ns t pzl , t pzh maximum propagation delay, enable to analog output (figures 13 and 14) 2.5 3.0 4.5 3.0 0 0 0 ?3.0 40 28 23 23 45 30 25 25 50 35 30 28 ns c pd power dissipation capacitance (figure 17) (note 6) typical @ 25 c, v cc = 5.0 v, v ee = 0 v 45 pf c in maximum input capacitance, channel?select or enable inputs 10 pf c i/o maximum capacitance analog i/o (all switches off) common o/i feedthrough 10 10 1.0 pf 6. used to determine the no?load dynamic power consumption: p d = c pd v cc 2 f + i cc v cc . additional application characteristics (gnd = 0 v) symbo l parameter condition v cc v v ee v typ unit 25 c bw maximum on?channel bandwidth or minimum frequency response v is = ? (v cc ? v ee ) ref and test attn = 10 db source amplitude = 0 db (figure 6) 3.0 4.5 6.0 3.0 0.0 0.0 0.0 ?3.0 80 80 80 80 mhz v iso off?channel feedthrough isolation f = 1 mhz; v is = ? (v cc ? v ee ) adjust network analyzer output to 10 dbm on each output from the power splitter. (figures 7 and 8) 3.0 4.5 6.0 3.0 0.0 0.0 0.0 ?3.0 ?70 ?70 ?70 ?70 db v onl maximum feedthrough on loss v is = ? (v cc ? v ee ) adjust network analyzer output to 10 dbm on each output from the power splitter. (figure 10) 3.0 4.5 6.0 3.0 0.0 0.0 0.0 ?3.0 ?2 ?2 ?2 ?2 db q charge injection v in = v cc to v ee, f is = 1 khz, t r = t f = 3 ns r is = 0 , c l = 1000 pf, q = c l * v out (figure 9) 5.0 3.0 0.0 ?3.0 9.0 12 pc thd total harmonic distortion thd + noise f is = 1 mhz, r l = 10 k , c l = 50 pf, v is = 5.0 v pp sine wave v is = 6.0 v pp sine wave (figure 18) 6.0 3.0 0.0 ?3.0 0.10 0.05 %
mc74lvxt4051 http://onsemi.com 6 figure 3. on resistance, test set?up plotter mini computer programmable power supply dc analyzer v cc device under test gnd analog in common out gnd figure 4. maximum off channel leakage current, any one channel, test set?up figure 5. maximum on channel leakage current, channel to channel, test set?up figure 6. maximum on channel bandwidth, test set?up off off 6 7 8 16 common o/i v cc v ih nc a v cc v ee v cc on off 6 7 8 16 common o/i v cc v il v cc v ee v cc n/c a analog i/o v ee v ee on off 6 7 8 v cc v ee 9?11 all untested analog i/o pins hp11667b pwr splitter hp4195a network anl 0.1 f s1 r1 t1 0.1 f 50 k 100 k v is a channel selects connected to address pins on hp4195a and appropriately configured to test each switch.
mc74lvxt4051 http://onsemi.com 7 figure 7. maximum off channel feedthrough isolation, test set?up figure 8. maximum common?channel feedthrough isolation, test set?up off on 6 7 8 v cc v ee 9?11 all untested analog i/o pins hp11667b pwr splitter hp4195a network anl 0.1 f s1 r1 t1 0.1 f 50 k 100 k v is 16 config = network format = t/r (db) cal = trans cal display = rectan x a b scale ref = auto scale view = off, off, off trig = cont mode source amplitude = 13 db reference attenuation = 20 db test attenuation = 0 db v iso (db) = 20 log (v t1 /v r1 ) 6 7 8 v cc v ee 9?11 all untested analog i/o pins hp11667b pwr splitter hp4195a network anl 0.1 f s1 r1 t1 0.1 f 50 100 k v is 16 config = network format = t/r (db) cal = trans cal display = rectan x a b scale ref = auto scale view = off, off, off trig = cont mode source amplitude = 13 db reference attenuation = 20 db test attenuation = 0 db v isoc (db) = 20 log (v t1 /v r1 ) on 50 k off channel selects connected to address pins on hp4195a and appropriately configured to test each switch. channel selects connected to address pins on hp4195a and appropriately configured to test each switch.
mc74lvxt4051 http://onsemi.com 8 figure 9. charge injection, test set?up on/off 7 8 v cc v out off/on 9?11 c l * v ih v il *includes all probe and jig capacitance. 16 bias channel selects to test each combination of analog inputs to common analog output. 6 enable v ee v in r is v is v out v out q = c l * v out figure 10. maximum on channel feedthrough on loss, test set?up off on 6 7 8 v cc v ee 9?11 all untested analog i/o pins hp11667b pwr splitter hp4195a network anl 0.1 f s1 r1 t1 0.1 f 50 100 k v is 16 config = network format = t/r (db) cal = trans cal display = rectan x a b scale ref = auto scale view = off, off, off trig = cont mode source amplitude = 13 db reference attenuation = 20 db test attenuation = 20 db v onl (db) = 20 log (v t1 /v r1 ) channel selects connected to address pins on hp4195a and appropriately configured to test each switch.
mc74lvxt4051 http://onsemi.com 9 figure 11. break?before?make, test set?up figure 12. break?before?make time on off 6 7 8 v cc v ee 9?11 tek 11801b dso com input 16 r l c l v in 50 v in 80% v cc t bbm 80% of v oh figure 13. propagation delays, channel select to analog out figure 14. propagation delay, test set?up channel select to analog out v cc gnd channel select analog out 50% t plh t phl 50% on/off 6 7 8 16 v cc c l * channel select test point common off/on analog i/o v cc on/off 6 7 8 enable v cc enable 90% 50% 10% t f t r v cc gnd analog out t pzl analog out t pzh high impedance v ol v oh high impedance 10% 90% t plz t phz 50% 50% analog i/o c l * test point 16 v cc 1 k 1 2 1 2 position 1 when testing t phz and t pzh position 2 when testing t plz and t pzl gnd gnd o/i channel selects connected to v in and appropriately configured to test each switch. v oh *includes all probe and jig capacitance. figure 15. propagation delays, enable to analog out figure 16. propagation delay, test set?up enable to analog out
mc74lvxt4051 http://onsemi.com 10 figure 17. power dissipation capacitance, test set?up on/off 12 v cc nc off/on 10 ? 11, 13 ? 14 channel select 15 v il v cc a figure 18. total harmonic distortion, test set?up 6 7 8 9?11 hp3466 dmm 16 50 k v com hp3466 dmm v com hp e3630a dc pwr supply com 20 v 20 v hp 339 distortion measurement set analyzer input com oscillator output com r l c l on off channel selects connected to dc bias supply or ground and appropriately configured to test each switch.
mc74lvxt4051 http://onsemi.com 11 applications information the channel select and enable control pins should be at v cc or gnd logic levels. v cc being recognized as a logic high and gnd being recognized as a logic low. in this example: v cc = 5 v = logic high gnd = 0 v = logic low the maximum analog voltage swing is determined by the supply voltages v cc and v ee . the positive peak analog voltage should not exceed v cc . similarly, the negative peak analog voltage should not go below v ee . in this example, the difference between v cc and v ee is five volts. therefore, using the configuration of figure 20, a maximum analog signal of five volts peak?to?peak can be controlled. unused analog inputs/outputs may be left floating (i.e., not connected). however, tying unused analog inputs and outputs to v cc or gnd through a low value resistor helps minimize crosstalk and feedthrough noise that may be picked up by an unused switch. although used here, balanced supplies are not a requirement. the only constraints on the power supplies are that: v ee ? gnd = 0 to 6 volts v cc ? gnd = 2.5 to 6 volts v cc ? v ee = 2.5 to 6 volts and v ee gnd when voltage transients above v cc and/or below v ee are anticipated on the analog channels, external germanium or schottky diodes (d x ) are recommended as shown in figure 21. these diodes should be able to absorb the maximum anticipated current surges during clipping. analog signal figure 19. application example on 6 7 8 16 analog signal 3.0 v 3.0 v 11 10 9 to external cmos circuitry 0 to 3.0 v digital signals figure 20. application example analog signal on 6 7 8 16 5 v analog signal 5 v gnd 5 v gnd 11 10 9 to external cmos circuitry 0 to 5 v digital signals on/off 7 8 16 v cc v ee d x v cc d x v ee d x v cc d x v ee figure 21. external germanium or schottky clipping diodes 3.0 v 3.0 v 3.0 v 3.0 v
mc74lvxt4051 http://onsemi.com 12 13 x0 14 x1 15 x2 12 x3 1 x4 5 x5 2 x6 4 x7 3 x level shifter level shifter level shifter level shifter 11 a 10 b 9 c 6 enable figure 22. function diagram, lvxt4051
mc74lvxt4051 http://onsemi.com 13 package dimensions tssop?16 case 948f issue b ??? ??? dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c ??? 1.20 ??? 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.18 0.28 0.007 0.011 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ?w?. section n?n seating plane ident. pin 1 1 8 16 9 detail e j j1 b c d a k k1 h g s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) ?t? ?v? ?w? 0.25 (0.010) 16x ref k n n 7.06 16x 0.36 16x 1.26 0.65 dimensions: millimeters 1 pitch soldering footprint* *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d.
mc74lvxt4051 http://onsemi.com 14 package dimensions soic?16 case 751b?05 issue k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p ?b? ?a? m 0.25 (0.010) b s ?t? d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019 6.40 16x 0.58 16x 1.12 1.27 dimensions: millimeters 1 pitch soldering footprint* 16 89 8x *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemni fy and hold scillc and its officers, em ployees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 mc74lvxt4051/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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